The present invention relates generally to multi-sheet conductive substrates for microelectronic devices. In particular, the invention relates to substrates formed from a plurality of sheets each having electrically conductive regions, wherein at least one sheet has both exposed and covered electrically conductive regions. Also provided are methods for forming multi-sheet conductive substrates.
To increase the portability of electronic products, there is an ongoing effort to miniaturize integrated circuits, processors, and other microelectronic devices such as semiconductor chips. Similarly, as there is a need to increase functionalities of such microelectronic devices, there is an ongoing effort to increase the number of input and output connections in microelectronic devices to other electronic components. As the number of interconnections per microelectronic device increases and the size of microelectronic devices decrease, the number of contacts per unit surface area of such devices increases. In addition, microelectronic devices are increasingly packaged in chip-scale and multi-chip packages to facilitate testing and connection to other electronic components of the electronic products. Such packages often employ prefabricated arrays or rows of leads/discrete wires, solder bumps or combinations of both on a substrate. In short, finer contact pitches are required to keep up with the demand for improved microelectronic devices and their corresponding packages.
Advances in microelectronic devices packaging have been accompanied by corresponding advances in the materials and technologies for use as package substrates. For example, early microelectronic devices have been packaged using metal leadframe substrates. Such substrates are generally well suited for lead counts of about 8 to about 48 contacts having a pitch of about 1.78 to about 2.54 mm. Later, rigid laminate substrates have been used to package microelectronic devices. Such substrates may include two to four alternating layers fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. When ball grid array (BGA) formats are used, microelectronic device packaging may have about 144 to about 900 contacts having pitch comparable or finer than the pitch associated with lead frame technologies.
Recently, tape BGA packing formats have been introduced to provide a thinner packaging solution. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, sheets of copper-on-polyimide are commonly used for fine-line and high-density electronic interconnection applications. Polyimide base films offer good thermal and chemical stability and a low dielectric constant. Copper having high tensile strength, ductility, and flexure have been advantageously used in both flexible circuit and chip scale packaging applications. In particular, medical, hard disk drive, and other applications often require line and space features 50 micrometers and finer. Sheets of copper of a small grain size on polyimide are particularly suited for such applications.
In addition, adhesiveless copper-on-polyimide sheets are now widely used in the production of flexible circuits, rigid-flex boards, chip scale packages and other electronic connection products. A typical sheet is constructed from a polyimide base film, a thin metal tiecoat, a seedcoat, and a layer of copper electrodeposited on the seedcoat. For example, continuous vacuum techniques may be used to deposit the tiecoat and seedcoat, successively, and roll-to-roll electrodeposition methods may build up the copper layer. The elimination of the adhesive layer substantially reduces weight and thickness, offering advantages in portable applications.
When a polyimide base film is provided having opposing major surfaces, one or both major surfaces may have conductive regions thereon. Generally, a single-sided sheet, i.e., a sheet formed from a polyimide base film having conductive regions on only a single major surface, is significantly less expensive than a double-sided sheet having conductive regions on both major surfaces. Double-sided sheets, however, may be needed when a single-sided sheet does not have sufficient surface area to contain the conductive regions needed for an intended application.
Often, sheets are stacked to produce multilayer wiring circuit boards. For example, U.S. Pat. Nos. 6,528,874 and 6,646,337, each to Iijima et al., describe methods for producing wiring boards for mounting electronic devices, such as integrated circuits (ICs) and large scale integrated circuits (LSI circuits). The wiring substrates are formed by selectively etching a copper foil laminate so as to form layers having posts of uniform height. The layers may be stacked to form wiring circuit boards. U.S. Pat. Nos. 6,372,620 and 6,617,236, each to Oosawa et al., describe methods similar to those methods described in the Iijima et al. patents for producing wiring boards. The Oosawa et al. methods, however, involve using the use of additive rather than subtractive processes to form the layers.
In addition, U.S. Patent Application Publication No. 20020140076 to Yamazaki et al. describes a compact multilayer wiring circuit board. The board includes first and second wiring circuit boards. The first board is made of a laminate of conductive and insulating layers. The second wiring circuit board includes at least one conductive layer and is laminated on a partial region of the first wiring circuit board. Only one insulating layer is interposed between an outermost conductive layer of the first wiring circuit board and the nearest conductive layer of the second wiring circuit board to the outermost conductive layer. Generally, the board may be produced by providing first and second laminates, each having conductive and insulating layers. The conductive surface layer of the first laminate is laminated on the insulating surface layer of the second laminate, and a partial region of the conductive layer of the second laminate is removed to expose the insulating surface layer thereof.
In order to connect the conductive regions of different layers of multilayer wiring circuit boards, one or more vias are typically formed through drilling or similar techniques. Via formation, however, can contribute significantly to the cost of circuit boards. In contrast, wire bonding and lead bonding techniques are, as a general matter, relatively inexpensive compared to via formation techniques.
Thus, there exist opportunities in the art to provide alternatives and improvements to substrate technologies for microelectronic device packaging application, particularly those technologies compatible with wire bonding and lead bonding techniques and those technologies that do not require formation of vias.